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asahi kasei [ak4112a] ms0020-e-00 2000/3 - 1 - general description the ak4112a is a digital audio receiver (dir) compatible with 96khz, 24bits. the channel status decoding supports both consumer and professional modes. the ak4112a can automatically detect a non-pcm bit stream. when combined with an ak4527 multi channel codec, the two chips provide a system solution for ac-3 applications. the dedicated pins or a serial up i/f can control the mode setting. the small package, 28pin vsop saves the board space. *ac-3 is a trademark of dolby laboratories. features o supports aes/ebu, iec958, s/pdif, eiaj cp1201 o low jitter analog pll o pll lock range : 22k ~ 108khz o clock source: pll or x'tal o 4 channel receivers input and 1 through transmission output o auxiliary digital input o de-emphasis for 32khz, 44.1khz, 48khz and 96khz o dedicated detect pins non-pcm bit stream detect pin validity flag detect pin 96khz sampling detect pin unlock & parity error detect pin o supports up to 24bit audio data format o audio i/f: master or slave mode o 32bits channel status buffer o burst preamble bit pc, pd buffer for non-pcm bit stream o serial p i/f o two master clock outputs:128fs/256fs/512fs o operating voltage: 2.7 to 3.6v with 5v tolerance o small package: 28pin vsop o ta: -40 ~ 85 c high feature 96khz 24bit dir ak4112a
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 2 - n n n n compatibility with AK4110 AK4110 ak4112a ambient temperature -20 ~ 85 c -40 ~ 85 c avdd, dvdd 3.0 ~ 3.6v 2.7 ~ 3.6v fs 32khz ~ 96khz 22khz ~ 108khz crystal resonator (max) 12.288mhz 24.576mhz clock operation mode 3 x o parallel control mode x o tx output x o 512fs output x o 384fs output o x burst preamble pc, pd buffers x o (0dh ~ 10h) fs96 output select in xtal mode x o (11h d0; xfs96) erf hold time fixed (1028/fs) selectable (512, 1024, 2048, 4096/fs) (11h d2, d1; erh1, erh0) input data format of daux mode5 and 7 not available i 2 s pin #7 r pdn pin #8 daux r pin #22 pdn daux resistor on r pin 9.1k w 18k w capacitor on r pin no need no need ( 100pf) o: available, x: not available
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 3 - input selector s y stem control clock recover y clock generator daif decoder ac-3/mpeg detect error detect dem p i/f audio i/f 96khz detect x'tal oscillator rx1 rx2 rx3 rx4 v/tx dvdd dvss pdn auto erf p/s="l" tvdd lrck bick sdto daux fs96 xto xti mcko2 mcko1 r avdd avss cdti cdto cclk csn serial control mode s y stem control clock recover y clock generator daif decoder ac-3/mpeg detect error detect dem audio i/f 96khz detect x'tal oscillator rx1 v dvdd dvss auto erf p/s="h" tvdd lrck bick sdto daux fs96 xto xti mcko2 mcko1 r avdd avss cm1 cm0 ocks1 ocks0 ocks0 pdn ocks1 cm0 cm1 dif0 dif1 dif2 4 parallel control mode
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 4 - n ordering guide ak4112avf -40 ~ +85 c 28pin vsop (0.65mm pitch) n n n n pin layout 6 5 4 3 2 1 dvdd dvss v/tx tvdd xti xto pdn 7 r 8 top view 10 9 avdd avss rx1 11 rx2/dif0 12 13 14 rx3/dif1 rx4/dif2 cm0/cdto cm1/cdti ocks1/cclk ocks0/csn mcko1 mcko2 daux bick sdto lrck erf fs96 23 24 25 26 27 28 22 21 19 20 18 17 16 15 p/sn auto
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 5 - pin/function no. pin name i/o function 1 dvdd - digital power supply pin, 3.3v 2 dvss - digital ground pin 3 tvdd - input buffer power supply pin, 3.3v or 5v v o validity flag output pin in parallel mode 4 tx o transmit channel (through data) output pin in serial mode 5xti i x'tal input pin 6 xto o x'tal output pin 7pdn i power-down mode pin when l, the ak4112a is powered-down and reset. 8r - external resistor pin 18k w +/-1% resistor to avss externally. 9 avdd - analog power supply pin 10 avss - analog ground pin 11 rx1 i receiver channel 1 this channel is selected in parallel mode or default of serial mode. dif0 i audio data interface format 0 pin in parallel mode 12 rx2 i receiver channel 2 in serial mode dif1 i audio data interface format 1 pin in parallel mode 13 rx3 i receiver channel 3 in serial mode dif2 i audio data interface format 2 pin in parallel mode 14 rx4 i receiver channel 4 in serial mode 15 auto o non-pcm detect pin l: no detect, h : detect 16 p/s i parallel/serial select pin l: serial mode, h: parallel mode 17 fs96 o 96khz sampling detect pin (rx mode) h : fs=88.2khz or more, l fs=54khz or less. (xtal mode) h : xfs96=1, l : xfs96=0. 18 erf o unlock & parity error output pin l: no error, h: error 19 lrck i/o output channel clock pin 20 sdto o audio serial data output pin 21 bick i/o audio serial data clock pin 22 daux i auxiliary audio data input pin 23 mck02 o master clock #2 output pin 24 mck01 o master clock #1 output pin ocks0 i output clock select 0 pin in parallel mode 25 csn i chip select pin in serial mode ocks1 i output clock select 1 pin in parallel mode 26 cclk i control data clock pin in serial mode cm1 i master clock operation mode pin0 in parallel mode 27 cdti i control data input pin in serial mode cm0 i master clock operation mode pin1 in parallel mode 28 cdto o control data output pin in serial mode note 1: all input pins except internal pull-down pins should not be left floating.
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 6 - absolute maximum ratings (avss, dvss=0v; note 2) parameter symbol min max units power supplies: analog digital input buffer |avss-dvss| (note 3) avdd dvdd tvdd d gnd -0.3 -0.3 -0.3 4.6 4.6 6.0 0.3 v v v v input current , any pin except supplies iin - 10 ma input voltage (except xti pin) input voltage (xti pin) vin vinx -0.3 -0.3 tvdd+0.3 dvdd+0.3 v v ambient temperature (power applied) ta -40 85 c storage temperature tstg -65 150 c note 2: all voltages with respect to ground. note 3: avss and dvss must be connected to the same ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v;note 2) parameter symbol min typ max units power supplies: analog digital input buffer avdd dvdd tvdd 2.7 2.7 dvdd 3.3 3.3 3.3 3.6 avdd 5.5 v v v note 2: all voltages with respect to ground. s/pdif receiver characteristics (ta=25 c; avdd, dvdd=2.7~3.6v;tvdd=2.7~5.5v) parameter symbol min typ max units input resistance zin 10 k w input voltage vth 350 mvpp input hysteresis vhy - 130 mv input sample frequency fs 22 - 108 khz dc characteristics (ta=25 c; avdd, dvdd=2.7~3.6v;tvdd=2.7~5.5v; unless otherwise specified) parameter symbol min typ max units power supply current normal operation : pdn = h (note 4) power down: pdn = l (note 5) 20 10 40 100 ma m a high-level input voltage (except xti pin) high-level input voltage (xti pin) low-level input voltage vih vih vil 70%dvdd 70%dvdd dvss-0.3 - - - tvdd dvdd 30%dvdd v v v high-level output voltage (iout=-400 m a) low-level output voltage (iout=400 m a) voh vol dvdd-0.4 - - - - 0.4 v v input leakage current iin - - 10 m a note 4: avdd, dvdd=3.3v, tvdd=5.0v, c l =20pf, fs=96khz, x'tal=12.288mhz, clock operation mode 2, ocks1=1, ocks0=0. avdd=8ma(typ), dvdd=12ma(typ), tvdd=10 m a(typ) note 5: rx inputs are open and all digital input pins are held dvdd or dvss.
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 7 - switching characteristics (ta=25 c; dvdd, avdd2.7~3.6v, tvdd=2.7~5.5v; c l =20pf) parameter symbol min typ max units master clock timing crystal resonator frequency fxtal 11.2896 24.576 mhz external clock frequency duty feclk declk 11.2896 40 50 24.576 60 mhz % mcko1 output frequency duty fmck1 dmck1 5.632 40 50 27.648 60 mhz % mcko2 output frequency duty fmck2 dmck2 2.816 40 50 27.648 60 mhz % pll clock recover frequency (rx1-4) fpll 22 - 108 khz lrck frequency duty cycle fs dlck 22 45 48 108 55 khz % audio interface timing slave mode bick period bick pulse width low pulse width high lrck edge to bick - (note 6) bick - to lrck edge (note 6) lrck to sdto (msb) bick to sdto daux hold time daux setup time tbck tbckl tbckh tlrb tblr tlrm tbsd tdxh tdxs 140 60 60 30 30 20 20 35 35 ns ns ns ns ns ns ns ns ns master mode bick frequency bick duty bick to lrck bick to sdto daux hold time daux setup time fbck dbck tmblr tbsd tdxh tdxs -20 20 20 64fs 50 20 40 hz % ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn h time csn to cclk - cclk " - " to csn - cdto delay csn - to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 150 50 50 45 70 ns ns ns ns ns ns ns ns ns ns reset timing pdn pulse width tpw 150 ns note 6: bick rising edge must not occur at the same time as lrck edge.
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 8 - n timing diagram tlrb lrck bick sdto tbsd tblr tbckl tbckh tlrm 50%dvdd 50%dvdd 50%dvdd daux 50%dvdd tdxs tdxh serial interface timing (slave mode) lrck bick sdata tbsd tmblr 50%dvdd 50%dvdd 50%dvdd daux tdxh 50%dvdd tdxs serial interface timing (master mode) tcckl csn cclk tcds cdti tcdh tcss c0 a4 tcckh cdto hi-z r/w c0 50%dvdd 50%dvdd 50%dvdd write/read command input timing
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 9 - tcsw csn cclk cdti d2 d0 tcsh cdto hi-z d1 d3 50%dvdd 50%dvdd 50%dvdd write data input timing csn cclk tdcd cdto d7 d6 cdti a1 a0 d5 hi-z 50%dvdd 50%dvdd 50%dvdd 50%dvdd read data output timing 1 csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%dvdd 50%dvdd 50%dvdd 50%dvdd read data input timing 2 tpw pdn 30%dvdd power down & reset timing
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 10 - operation overview n n n n non-pcm (ac-3, mpeg, etc.) stream detect the ak4112a has a non-pcm steam auto detect function. when the 32bit mode non-pcm preamble based on dolby ac-3 data stream in iec958 interface is detected, the auto goes h. the 96bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872 and 0x4e1f. detection of this pattern will set the auto h. once the auto is set h, it will remain h until 4096 frames pass through the chip without additional sync pattern being detected. when those preambles are detected, the burst preambles pc and pd that follow those sync codes are stored to registers 0dh- 10h. n n n n clock recovery and 96khz detect on chip low jitter pll has a wide lock range with 22khz to 108khz and the lock time is less than 20ms. the 96khz detect output pin fs96 goes h when the sampling rate is 88.2khz or more and l at 54khz or less. in xtal mode, the fs96 pin outputs the value which is set by xfs96. pll loses lock when the received sync interval is incorrect. n n n n master clock the ak4112a has two clock outputs, mcko1 and mcko2. these clocks are derived from either the recovered clock or from the x'tal oscillator. the frequencies of the master clock outputs (mcko1 & mcko2) are set by ocks0 and ocks1 as shown in table 1. 96khz sampling is not supported at no.2. no. ocks1 ocks0 mcko1 mcko2 xtal fs (khz) 0 0 0 256fs 256fs 256fs 32, 44.1, 48, 96 defalt 1 0 1 256fs 128fs 256fs 32, 44.1, 48, 96 2 1 0 512fs 256fs 512fs 32, 44.1, 48 3 1 1 test mode table 1. master clock frequencies select n n n n clock operation mode the cm0 and cm1 select the clock source of mcko1/2 and the data source of sdto via the dedicated pins or the control register. in mode 2, the clock source is switched from pll to x'tal when pll goes unlock state. in mode3, the clock source is fixed to x'tal, but pll is also operating and the recovered data such as c bits can be monitored. mode cm1 cm0 unlock pll x'tal clock source fs96 sdto 0 0 0 - on off pll rfs96 rx default 101 - off on x'tal xfs96 daux 0 on on pll rfs96 rx 210 1 on on x'tal xfs96 daux 3 1 1 - on on x'tal xfs96 daux on: oscillation (power-up), off: stop (power-down) table 2. clock operation mode select
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 11 - n n n n clock source the following circuits are available to feed the clock to xti pin (#5 pin) of ak4112a. 1) xtal note: external capacitance depends on the crystal oscillator (typ. 10-40pf) 2) external clock note: input clock must not exceed dvdd. 3) fixed to the clock operation mode 0 xti xto ak4112a xti xto ak4112a external clock xti xto ak4112a
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 12 - n n n n sampling frequency and pre-emphasis detect the ak4112a outputs the encoded information of sampling frequency and pre-emphasis in channel status to fs0, fs1 and pem bits in control register. these information are output from channel 1 at default. it can be switched to channel 2 by cs12 bit in control register. fs1 fs0 fs byte 3 bits 0-3 0 0 44.1khz 0000 0 1 reserved all others 1 0 48khz 0100 1 1 32khz 1100 table 3. fs information in consumer mode fs1 fs0 fs byte 0 bits 6-7 0 0 44.1khz 10 01reserved00 1 0 48khz 01 1 1 32khz 11 table 4. fs information in profession mode pem pre-emphasis byte 0 bits 3-5 0off 1 0x100 1 on 0x100 table 5. pem in consumer mode pem pre-emphasis byte 0 bits 2-4 0off 1 110 1 on 110 table 6. pem in professional mode
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 13 - n n n n de-emphasis filter control the ak4112a includes the digital de-emphasis filter (tc=50/15s) by iir filter corresponding to four sampling frequencies (32khz, 44.1khz, 48khz and 96khz). when deau bit=1, the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. the ak4112a goes this mode at default. therefore, in parallel mode, the ak4112a is always placed in this mode and the de-emphasis filter is controlled by the status bits in channel 1. in serial mode, dem0/1 and dfs bits can control the de-emphasis filter when deau is 0. the internal de-empahsis filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis mode is off. fs96 fs1 fs0 mode 0 0 0 44.1khz 001off 0 1 0 48khz 0 1 1 32khz 100off 101off 1 1 0 96khz 111off table 7. de-emphasis auto control at deau=1 and pem=1 dfs dem1 dem0 mode 0 0 0 44.1khz 001offdefault 0 1 0 48khz 0 1 1 32khz 100off 101off 1 1 0 96khz 111off table 8. de-emphasis manual control at deau=0 and pem=1
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 14 - n n n n system reset and power-down the ak4112a has a power-down mode for all circuits by pdn pin can be partially powerd-down by pwn bit. the rstn bit initializes the register and resets the internal timing. in parallel mode, only the control by pdn pin is enabled. the ak4112a should be reset once by bringing pdn pin = l upon power-up. pdn pin (pin #7): all analog and digital circuit are placed in the power-down and reset mode by bringing pdn= l. all the registers are initialized, and clocks are stopped. reading/witting to the register are diabled. rstn bit (address 00h; d0): all the registers except pwn and rstn are initialized by bringing rstn bit = 0. the internal timings are also initialized. witting to the register is not available except pwn and rstn. reading to the register is disabled. pwn bit (address 00h; d1): the clock recovery part is initialized by bringing pwn bit = 0. in this case, clocks are stopped. the registers are not initialized and the mode settings are kept. writing and reading to the registers are enabled. n n n n biphase input and through output four receiver inputs (rx1-4) are available in serial control mode. each input includes amplifier corresponding to unbalance mode and can accept the signal of 350mv or more. ips0-1 selects the receiver channel, and ops0-1 selects the source of the bit stream driving the transmit channel (tx). the tx output can be stopped by setting txe bit 0. ips1 ips0 input data 00 rx1default 01 rx2 10 rx3 11 rx4 table 9. recovery data select ops1 ops0 input data 00 rx1default 01 rx2 10 rx3 11 rx4 table 10. output data select
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 15 - rx ak4112a 0.1uf 75 w coax 75 w 0.47nf note figure 1. consumer input circuit (coaxial input) note: in case of coaxial input, if a coupling level to this input from the next rx input line pattern exceeds 50mv, there is a possibility to occur an incorrect operation. in this case, it is possible to lower the coupling level by adding this decoupling capacitor. rx ak4112a 470 o/e optical receiver optical fiber figure 2. consumer input circuit (optical input) in case of coaxial input, as the input level of rx line is small, in serial mode, be careful not to crosstalk among rx input lines. for example, by inserting the shield pattern among them. in parallel mode, only one channel input (rx1) is available and rx2-4 change to other pins for audio format control. those pins must be fixed to h or l. the ak4112a includes the tx output buffer. the output level meets combination 0.5v+/-20% using the external resistor network. the t1 in figure 3 is a transformer of 1:1. tx dvss r2 t1 75 w cable r1 vdd r1 r2 3.3v 240 w 150 w 3.0v 220 w 150 w figure 3. tx external resistor network
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 16 - n error handling there are the following five factors which erf pin goes h. erf pin shows the status of the internal pll operation and it is l when the pll is off (clock operation mode 1). 1. unlock error : h when the pll goes unlock state. 2. parity error : updated every sub-frame cycle. 3. biphase error : updated every sub-frame cycle 4. frame length error : updated every sub-frame cycle 5. stc (status change) flag=1 : holds 1 until reading 03h. in parallel mode, erf pin outputs the ored signal including the factors of 1,2,3 and 4. once erf pin goes h, it maintains h for 1024/fs cycles after the all error factors are removed. table 11 shows the state of each output pins when the erf pin is h. the frame length error is occurred when the interval of preamble in biphase signal is incorrect. when unlock state, the channel status bits are not updated and the previous data is maintained. error auto sdto v unlock error l l l parity error output previous data output biphase error output previous data output frame length error output previous data output table 11. error handling (parallel mode) in serial mode, erf pin outputs the ored signal including the factors of 1,2,3,4 and 5. however, parity, biphase and frame length error can be masked by mpar bit, and the stc flag can be masked by mstc bit. when those are masked by each bit, the error factor does not affect erf pin operation. the stc flag is set whenever a comparison between the last sample of bits d5-0 of the receiver status 1 register (03h) and the new sample are different this comparison is made every fs cycle. the stc flag is reset by reading the register 03h. this flag is also disabled during the first block after reset. once erf pin goes h, it maintains h for 1024/fs cycles (can be changed by erfh0-1 bits) after the all error factors (in case of stc, from stc flag 1 to reading 03h) are removed. once par, bip, frerr, v or unlock bit goes 1, it returns 0 by reading receiver status 2 (04h). when unlock state, the channel status bits are not updated and the previous data is maintained. register pin error & status unlock par bip frerr stc auto sdto v tx unlock error 1 0 0 0 0 l l l output parity error 0 1 0 0 0 output previous data output output biphase error 0 0 1 0 0 output previous data output output frame length error 0 0 0 1 0 output previous data output output status change 0 0 0 0 1 output output output output table 12. error handling (serial mode; mpar=1, mstc=1)
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 17 - command erf mcko, bick, lrck sdto stc bit v read 03h reset (ch. status ) (state b) (state a ) (status change ) erf hold time hold 1 erf pin timing at status change error(unlock, par, bip, frerr) erf sdto(unlock) vpin (unlock) mcko,bick,lrck (unlock) vpin (except unlock) previous data register (unock, par, bip, frerr) hold 1 command read 04h mcko,bick,lrck (except unlock) (fs: around 20khz) sdto (except unlock) erf hold time reset (error) erf pin timing at unlock, par, bip, frerr error
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 18 - pd pin ="l" to "h" read 03h stc is reset, erf pin ="l" read 04h mute = "h" erf pin ="h" read 03h stc is reset, erf pin ="l" read 04h erf pin ="h" mute="l" no yes yes initialize figure 4. error handling sequence example
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 19 - n audio serial interface format the dif0, dif1 and dif2 pins as shown in table 13 can select eight serial data formats. in all formats the serial data is msb-first, 2's compliment format. the sdto is clocked out on the falling edge of bick and the daux is latched on the rising edge of bick. bick outputs 64fs clock in mode 0-5. mode 6-7 are slave modes, and bick is available up to 128fs at fs=48khz. in the format equal or less than 20bit (mode0-2), lsbs in sub-frame are truncated. in mode 3-7, the last 4lsbs are auxiliary data (see figure 5). when the parity error, biphase error or frame length error occurs in a sub-frame, ak4112a continues to output the last normal sub-frame data from sdto repeatedly until the error is removed. when the unlock error occurs, ak4112a output 0 from sdto. in case of using daux pin, the data is transformed and output from sdto. daux pin is used in clock operation mode 1, 3 and unlock state of mode 2. the input data format to daux should be left justified except in mode5 and 7(table 13). in mode5 or 7, both the input data format of daux and output data format of sdto are i 2 s. mode6 and 7 are slave mode that is corresponding to the master mode of mode4 and 5. in salve mode, lrck and bick should be fed with synchronizing to mcko1/2. the initial state of the audio format is the master mode upon the power-up. therefore, if the audio format is changed to the slave mode after power-up, the setting of the external clocks should be careful until completing to set the control registers. 0 34 7 811 12 27 28 29 30 31 preamble aux. lsb msb vucp sub-frame of iec958 0 23 ak4112 audio data (msb first) lsb msb figure 5. bit configuration lrck bick mode dif2 dif1 dif0 daux sdto i/o i/o 0 0 0 0 24bit, left justified 16bit, right justified h/l o 64fs o 1 0 0 1 24bit, left justified 18bit, right justified h/l o 64fs o 2 0 1 0 24bit, left justified 20bit, right justified h/l o 64fs o 3 0 1 1 24bit, left justified 24bit, right justified h/l o 64fs o 4 1 0 0 24bit, left justified 24bit, left justified h/l o 64fs o default 5 10124bit, i 2 s 24bit, i 2 s l/h o 64fs o 6 1 1 0 24bit, left justified 24bit, left justified h/l i 64-128fs i 7 11124bit, i 2 s 24bit, i 2 s l/h i 64-128fs i table 13. audio data format
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 20 - lrck(0) bick ( 0:64fs ) sdto ( 0 ) 012 31 0 1 15:msb, 0:lsb lch data rch data 15 17 16 15 31 0 1 2 17 16 010 1 15 14 14 15 figure 5. mode 0 timing lrck ( 0 ) bick ( 0:64fs ) sdto ( 0 ) 012 31 0 1 23:msb, 0:lsb lch data rch data 911 10 9 31 0 1 2 11 10 010 1 12 21 20 20 21 12 22 23 22 23 figure 6. mode 3 timing lrck bick ( 64fs ) sdto ( 0 ) 012 31 0 1 23:msb, 0:lsb lch data rch data 21 23 22 21 31 0 1 2 23 22 23 22 2 24 1 0 0 1 24 21 22 23 32 23 22 figure 7. mode 4, 6 timing mode 4: lrck, bick: output mode 6: lrck, bick: input lrck bick ( 64fs ) sdto ( 0 ) 012 31 0 1 23:msb, 0:lsb lch data rch data 23 22 21 31 0 1 2 23 22 23 22 24 1 0 24 32 23 25 2 0 1 21 22 23 25 figure 8. mode 5, 7 timing mode 5: lrck, bick: output mode 7: lrck, bick: input
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 21 - n n n n serial control interface the internal registers may be either written or read by the 4-wire p interface pins: csn, cclk, cdti & cdto. the data on this interface consists of chip address (2bits, c0/1 are fixed to 00), read/write (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after the 16th rising edge of cclk, after a high-to-low transition of csn. for read operations, the cdto output goes high impedance after a low-to-high transition of csn. the maximum speed of cclk is 5mhz. the csn and cclk must be fixed to h when the register does not be accessed. pdn= l resets the registers to their default values. when the state of p/s pin is changed, the ak4112a should be reset by pdn= l. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 cdto hi-z write cdti c1 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 cdto hi-z read d4 d5 d6 d7 d0 d1 d2 d3 hi-z c1-c0: chip address (fixed to 00) r/w: read/write (0:read, 1:write) a4-a0: register address d7-d0: control data figure 10. control i/f timing
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 22 - n register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clock & power down control 0 bcu cm1 cm0 ocks1 ocks0 pwn rstn 01h input/output control mpar mstc cs12 txe ips1 ips0 ops1 ops0 02h format & de-emphasis control v/tx dif2 dif1 dif0 deau dem1 dem0 dfs 03h receiver status 1 erf 0 audion auto pem fs1 fs0 rfs96 04h receiver status 2 cv stc crc unlock v frerr bip par 05h channel a status byte 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 06h channel a status byte 1 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 07h channel a status byte 2 ca23 ca22 ca21 ca20 ca19 ca18 ca17 ca16 08h channel a status byte 3 ca31 ca30 ca29 ca28 ca27 ca26 ca25 ca24 09h channel b status byte 0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 0ah channel b status byte 1 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 0bh channel b status byte 2 cb23 cb22 cb21 cb20 cb19 cb18 cb17 cb16 0ch channel b status byte 3 cb31 cb30 cb29 cb28 cb27 cb26 cb25 cb24 0dh burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0eh burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 0fh burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 10h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 11h count control 0 0 0 0 0 efh1 efh0 xfs96 notes: for addresses from 12h to 1fh, data must not be written. when pdn pin goes l, the registers are initialized to their default values. when rstn bit goes 0, the internal timing is reset and the registers are initialized to their default values. all data can be written to the register even if pwn bit is 0.
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 23 - n n n n register definitions reset & initialize addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clock & power down control 0 bcu cm1 cm0 ocks1 ocks0 pwn rstn r/w rd r/w r/w r/w r/w r/w r/w r/w default 00000011 rstn: timing reset & register initialize 0: reset & initialize 1: normal operation pwn: power down 0: power down 1: normal operation ocks1-0: master clock frequency select cm1-0: master clock operation mode select bcu: block start & c/u output mode when bcu=1, the 3 output pins change another function. mcko2 pin ? b; block start signal auto pin ? c bit fs96 pin ? u bit the block signal goes high at the start of frame 0 and remains high until the end of frame 31. (b, c, u, v output timing at rx mode, master mode) b c (or u,v) lrck c(l0) c(r0) c(l1) c(r31) c(l31) c(l32) c(r191) 1/4fs sdto (except i 2 s) l191 r191 l0 r30 r31 l31 sdto (i 2 s) l191 r191 l30 l31 r30 l0 r190 r0
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 24 - input/output control addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h input/output control mpar mstc cs12 txe ips1 ips0 ops1 ops0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 10010000 ops1-0: output through data select ips1-0: input recovery data select txe: tx output enable 0: disable. tx output pin is placed in a high impedance state. 1: enable cs12: channel status select 0: channel 1 1: channel 2 selects which channel status is used to derive audion, pem, fs1 and fs0. the de-emphasis filter, however, is always controlled by channel 1 in the parallel mode. mstc: status change flag mask bit this bit is low to mask status change from being reported by erf. mpar: parity mask bit this bit is low to mask parity error, biphase error and frame length error from being reported by erf. format & de-emphasis control addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h format & de-emphasis control v/tx dif2 dif1 dif0 deau dem1 dem0 dfs r/w r/w r/w r/w r/w r/w r/w r/w r/w default 01001010 v/tx: v/tx output select 0: validity flag output. this output is updated every fs cycle. 1: tx dfs: 96khz de-emphasis control dem1-0: 32, 44.1, 48khz de-emphasis control deau: de-emphasis auto detect enable 0: disable 1: enable dif2-0: audio data format control
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 25 - receiver status 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h receiver status 1 erf 0 audion auto pem fs1 fs0 rfs96 r/w rdrdrdrdrdrdrdrd default 00000000 rfs96: 96khz sampling detect at recovery mode. 0: fs=54khz or less. 1: fs=88.2khz or more fs1-0: sampling frequency output pem: pre-emphasis output 0: off 1: on this bit is made by encoding channel status bits. auto: non-pcm auto detect 0: no detect 1: detect this function is the same as auto pin. audion: audio bit output 0: audio 1: non audio erf: unlock or parity error or status change 0: no error or no change 1: error or change this function is the same as erf pin. this bit goes 1 when unlock error, parity error, biphase error, frame length error or status change occurs. if mpar=0 & mstc=0, only an unlock error is reported. receiver status 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h receiver status 2 cv stc crc unlock v frerr bip par r/w rdrdrdrdrdrdrdrd default 00000000 par: parity status (0:no error, 1:error) it is high if parity error is detected in the sub-frame. par is unaffected by the state of mpar. bip: biphase status (0:no error, 1:error) frerr: frame error status (0:no error, 1:error) v: validity bit (0:no error, 1:error) unlock: pll lock status (0:lock, 1:unlock) crc: cyclic redundancy check (0:no error, 1:error on either channel) stc: status change flag of receiver status 1 (0:no change, 1:change) this flag goes h when the latest value of d5-0 in receiver status 1(03h) is different from the previous value. this comparison is made at every fs cycle. this bit returns to l by reading receiver status 1(03h). the flag is disabled during the first block after reset. cv: channel status validity (0:valid, 1:not valid, data is updating) this signal goes h at the start of frame 0 and maintains h until the end of frame 31.
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 26 - channel status addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h channel a status byte 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 06h channel a status byte 1 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 07h channel a status byte 2 ca23 ca22 ca21 ca20 ca19 ca18 ca17 ca16 08h channel a status byte 3 ca31 ca30 ca29 ca28 ca27 ca26 ca25 ca24 09h channel b status byte 0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 0ah channel b status byte 1 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 0bh channel b status byte 2 cb23 cb22 cb21 cb20 cb19 cb18 cb17 cb16 0ch channel b status byte 3 cb31 cb30 cb29 cb28 cb27 cb26 cb25 cb24 r/w rd default not initialized ca31-0: channel a status byte 4-1 cb31-0: channel b status byte 4-1 bit definition changes depending upon pro bit setting. when cv=1, these bits are updating and may be invalid. burst preamble pc/pd in non-pcm encoded audio bitstreams addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0eh burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 0fh burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 10h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 r/w rd default not initialized pc15-0: burst preamble pc byte 1, 0 pd15-0: burst preamble pd byte 1, 0 count control addr register name d7 d6 d5 d4 d3 d2 d1 d0 11hcount control 00000efh1efh0xfs96 r/w rdrdrdrdrdr/wr/wr/w default 00000010 xfs96: fs96 output select at xtal mode (clock operation mode1, mode3 and unlock state of mode2) 1: fs96pin=h 0: fs96pin=l efh1-0: error flag hold count select 00: 512 lrck 01: 1024 lrck 10: 2048 lrck 11: 4096 lrck
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 27 - n n n n burst preambles in non-pcm bitstreams 0 16 bits of bitstream 34 7 811 12 27 28 29 30 31 preamble aux. lsb msb v u c p sub-frame of iec958 015 pa pb pc pd burst_payload stuffing repetition time of the burst preamble word length of field contents value pa 16 bits sync word 1 0xf872 pb 16 bits sync word 2 0x4e1f pc 16 bits burst info see table 15. pd 16 bits length code numbers of bits table 14. burst preamble words bits of pc value contents repetition time of burst in iec958 frames 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14-26 27 28 29-31 data type null data dolby ac-3 data reserved pause mpeg-1 layer1 data mpeg-1 layer2 or 3 data or mpeg-2 without extension mpeg-2 data with extension reserved mpeg-2, layer1 low sample rate mpeg-2, layer2 or 3 low sample rate reserved dts type i dts type ii dts type iii reserved (reserved for mpeg-4 aac data) mpeg-2 aac data reserved 4096 1536 384 1152 1152 384 1152 512 1024 2048 512 1024 5, 6 0 reserved, shall be set to 0 70 1 error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors 8-12 data type dependent info 13-15 0 bit stream number, shall be set to 0 table 15. fields of burst info pc
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 28 - n n n n non-pcm bitstream timing 1) when non-pcm preamble is not coming within 4096 frames, pa pc 1 pd 1 pb pa pc 2 pd 2 pb pa pc 3 pd 3 pb 0 pc 1 pc 2 0 pd 1 pd 2 pd 3 pc 3 pdn pin bit stream auto pc register pd register repetition time >4096 frames 2) when non-pcm bitstream stops pa pc 1 pd 1 pb stop pa pc n pd n pb pc 0 pc 1 pd 0 pd 1 pd n pc n erf pin bit stream auto pc register pd register erf hold time 2~3 syncs (b,m or w) <20ms (lock time) asahi kasei [ak4112a] ms0020-e-00 2000/3 - 29 - system design figure 11 shows the example of system connection diagram for serial mode. dvdd 1 dvss 2 tvdd 3 v/tx 4 xti 5 xto 6 pdn 7 r 8 avdd 9 avss 10 rx1 11 rx2 12 cdto 28 cdti 27 cclk 26 csn 25 mcko1 24 mcko2 23 daux 22 bick 21 sdto 20 lrck 19 erf 18 fs96 17 0.1u 10u + ak4112a 13 14 16 15 rx3 rx4 p/sn auto 3.3v supply 0.1u 10u + 18k (see figure 1,2) dsp and ad/da micro- controller 3.3~5v supply (note 8) c 10u + 0.1u 3.3v supply c figure 11. typical connection diagram (serial mode) notes: - c depends on the crystal oscillator (typ. 10-40pf) - avss and dvss must be connected the same ground plane - digital signals, especially clocks, should be kept away from the r pin in order to avoid an effect to the clock jitter performance.
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 30 - package 1.0 0.1 0.1 0-10 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.15-0.05 0.22 0.1 0.65 *9.8 0.2 1.25 0.2 a 1 14 15 28 28pin vsop ( unit: mm ) *5.6 0.2 7.6 0.2 0.5 0.2 +0.1 0.675 n n n n material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [ak4112a] ms0020-e-00 2000/3 - 31 - marking akm ak4112avf xxxb yyyyc xxxxbyyyyc: date code identifier xxxb: lot number (x : digit number, b : alpha character ) yyyyc: assembly date (y : digit number c : alpha character) important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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